Belgian semiconductor research centre imec and Lam Research have expanded their strategic partnership to tackle manufacturing challenges in advanced 3D chip integration and next-generation lithography as demand for AI computing infrastructure accelerates.<\/p>\n\n\n\n
The collaboration targets technologies needed to increase processor performance, memory bandwidth and energy efficiency as conventional transistor scaling becomes increasingly difficult.<\/p>\n\n\n\n
Researchers will investigate manufacturing processes supporting advanced packaging, heterogeneous integration and future memory architectures, combining Lam’s deposition and etching technologies with imec’s semiconductor research infrastructure.<\/p>\n\n\n\n
Key research areas include thick dielectric deposition, stress compensation, plasma dicing and high-aspect-ratio etching for increasingly complex three-dimensional memory structures.<\/p>\n\n\n\n
The partnership also extends to Lam’s Aether dry resist technology, designed for high-numerical-aperture extreme ultraviolet lithography, or high-NA EUV.<\/p>\n\n\n\n
Using imec’s advanced lithography facilities, researchers will examine improvements in pattern resolution, sensitivity and defect reduction for future semiconductor manufacturing nodes.<\/p>\n\n\n\n
Previous joint research demonstrated single-exposure patterning of ruthenium interconnects at 20-nanometre pitch, achieving 100% electrical yield for bridge-sensitive test structures and more than 90% for break-sensitive structures.<\/p>\n\n\n\n
The companies believe these results could reduce complex multi-patterning requirements while improving manufacturing efficiency.<\/p>\n\n\n\n
Further development will investigate advanced interconnects and semiconductor architectures, including gate-all-around transistors and complementary field-effect transistors.<\/p>\n\n\n\n
The expanded programme reflects growing industry pressure to move emerging semiconductor technologies beyond laboratory demonstrations into commercially viable production.<\/p>\n\n\n\n
Neither company disclosed financial terms or a timetable for industrial deployment.<\/p>\n\n\n\n
For chipmakers, the central challenge remains translating increasingly sophisticated research into reliable, scalable manufacturing processes.<\/p>\n","protected":false},"excerpt":{"rendered":"
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