HUAWEI has announced a new principle for guiding the future development of the semiconductor industry: the Tau (τ) Scaling Law. He Tingbo from HUAWEI delivered a keynote speech at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS), titled ‘New Semiconductor Path in Practice’, where she presented the law.
The Tau (τ) Scaling Law – also referred to as ‘Her’s Law’, named after Tingbo by peers and her colleagues – proposes replacing geometric scaling with time (τ) scaling as a new guiding principle for the evolution of both semiconductors and electronic systems. Based on this principle, innovative technologies such as LogicFolding can be used to continuously compress signal propagation delay and steadily improve transistor density, which will drive the ongoing evolution of semiconductors and electronic systems.
For more than five decades, Moore’s Law has been responsible for guiding and influencing the semiconductor industry but has faced severe physical limitations and diminishing economic returns. Such challenges have caused the wider industry to become increasingly constrained by the slowdown in the geometric scaling of transistors and the erosion of cost-per-transistor benefits. The industry must now tackle the urgent and common challenge of overcoming the physical constraints of traditional processes and find a new, sustainable evolution path that can match surging computing demands. This is where the τ Scaling Law comes into its own.
With the law front of mind, HUAWEI has developed innovative core technologies like LogicFolding and established a multi-level co-optimisation mechanism that spans semiconductor devices, circuits, chips and systems. This mechanism aims to systematically shorten the time constant τ in order to drive up performance, energy efficiency and transistor density at each level in the following ways:
- At the device level: Optimising the resistance and parasitic capacitance of transistors and interconnects to minimise the device-level time constant τ at the underlying physical layer.
- At the circuit level: Adopting the LogicFolding architecture to break down the physical boundaries of traditional circuit layouts, significantly shortening critical-path wiring, effectively reducing the resistive and capacitive load of signal propagation and ultimately boosting transistor density and circuit performance.
- At the chip level: Employing full-stack coordinated design of software, architecture and silicon to achieve fine-grained, workload-driven control over instruction and data flows, enhancing system-level parallelism and efficiency and significantly reducing end-to-end execution time.
- At the system level: Redefining interconnect protocols for computing systems with UnifiedBus to achieve unified memory addressing and native memory semantics for SuperPoDs, significantly reducing system communications latency.
HUAWEI’s application of the τ Scaling Law extends to smartphones and AI computing. Over the past six years, HUAWEI has designed and mass-produced 381 chips based on the law, serving a wide range of industries, sectors and markets. The Kirin chips scheduled to launch in Autumn 2026 will be the first ever to adopt the LogicFolding architecture, which will considerably enhance the chips’ performance. By 2031, the high-end chips HUAWEI designs based on the τ Scaling Law are expected to feature a transistor density that is equivalent to 14 Å (1.4 nm) processes.
Looking ahead, Tingbo outlined how openness and collaboration are key to driving ongoing progress in the semiconductor industry. She emphasised that no single company can independently find all the answers along the path of semiconductor evolution. With the τ Scaling Law, HUAWEI is excited to collaborate closely with scientists, engineers and industry partners around the world to drive the sustainable development of the semiconductor and electronics industries.
